#ifndef _FH8626V100_H_
#define _FH8626V100_H_


#define RAM_BASE			(0x10000000)
#define DDR_BASE			(0xA0000000)

#define PMU_REG_BASE			(0xF0000000)
#define TIMER_REG_BASE			(0xF0C00000)
#define GPIO0_REG_BASE			(0xF0300000)
#define GPIO1_REG_BASE			(0xF4000000)
#define UART0_REG_BASE			(0xF0700000)
#define UART1_REG_BASE			(0xF0800000)
#define UART2_REG_BASE			(0xF1300000)
#define SPI0_REG_BASE			(0xF0e00000)
#define SPI1_REG_BASE			(0xF0500000)
#define INTC_REG_BASE			(0xE0200000)
#define GMAC_REG_BASE			(0xE0600000)
#define USBC_REG_BASE			(0xE0700000)
#define DMAC_REG_BASE			(0xE0300000)
#define I2C1_REG_BASE			(0xF0B00000)
#define I2C0_REG_BASE			(0xF0200000)
#define I2C2_REG_BASE			(0xF0100000)
#define SDC0_REG_BASE			(0xE2000000)
#define SDC1_REG_BASE			(0xE2200000)
#define WDT_REG_BASE			(0xF0D00000)
#define PWM_REG_BASE			(0xF0400000)
#define I2S_REG_BASE			(0xF0900000)
#define ACW_REG_BASE			(0xF0A00000)
#define SADC_REG_BASE			(0xF1200000)
#define EFUSE_REG_BASE			(0xF1600000)
#define AES_REG_BASE			(0xE8200000)
#define RTC_REG_BASE			(0xF1500000)
#define DDRC_REG_BASE			(0xED000000)
#define CONSOLE_REG_BASE		UART0_REG_BASE


#define FH_PMU_REG_SIZE	0x2100

// SCU Register
#define REG_PMU_CHIP_ID              (0x0000)
#define REG_PMU_IP_VER               (0x0004)
#define REG_PMU_FW_VER               (0x0008)
#define REG_PMU_SYS_CTRL             (0x000c)
#define REG_PMU_PLL0                 (0x0010)
#define REG_PMU_PLL1                 (0x0014)
#define REG_PMU_CLK_GATE0            (0x001c)
#define REG_PMU_CLK_GATE1            (0x0020)
#define REG_PMU_CLK_GATE2            (0x0024)
#define REG_PMU_CLK_SEL              (0x0028)
#define REG_PMU_CLK_DIV0             (0x002c)
#define REG_PMU_CLK_DIV1             (0x0030)
#define REG_PMU_CLK_DIV2             (0x0034)
#define REG_PMU_CLK_DIV3             (0x0038)
#define REG_PMU_CLK_DIV4             (0x003c)
#define REG_PMU_CLK_DIV5             (0x0040)
#define REG_PMU_CLK_DIV6             (0x0044)
#define REG_PMU_I2SCLK_CTRL          (0x0048)
#define REG_PMU_SWRST_MAIN_CTRL      (0x004c)
#define REG_PMU_SWRST_AXI_CTRL       (0x0050)
#define REG_PMU_SWRST_AHB_CTRL       (0x0054)
#define REG_PMU_SWRST_APB_CTRL       (0x0058)
#define REG_PMU_SPC_IO_STATUS        (0x005c)
#define REG_PMU_SPC_FUN              (0x0060)

#define REG_PMU_PAD_CIS_HSYNC_CFG        (0x0080)
#define REG_PMU_PAD_CIS_VSYNC_CFG        (0x0084)
#define REG_PMU_PAD_CIS_PCLK_CFG         (0x0088)
#define REG_PMU_PAD_CIS_D_0_CFG          (0x008c)
#define REG_PMU_PAD_CIS_D_1_CFG          (0x0090)
#define REG_PMU_PAD_CIS_D_2_CFG          (0x0094)
#define REG_PMU_PAD_CIS_D_3_CFG          (0x0098)
#define REG_PMU_PAD_CIS_D_4_CFG          (0x009c)
#define REG_PMU_PAD_CIS_D_5_CFG          (0x00a0)
#define REG_PMU_PAD_CIS_D_6_CFG          (0x00a4)
#define REG_PMU_PAD_CIS_D_7_CFG          (0x00a8)
#define REG_PMU_PAD_CIS_D_8_CFG          (0x00ac)
#define REG_PMU_PAD_CIS_D_9_CFG          (0x00b0)
#define REG_PMU_PAD_CIS_D_10_CFG         (0x00b4)
#define REG_PMU_PAD_CIS_D_11_CFG         (0x00b8)
#define REG_PMU_PAD_MAC_RMII_CLK_CFG     (0x00bc)
#define REG_PMU_PAD_MAC_REF_CLK_CFG      (0x00c0)
#define REG_PMU_PAD_MAC_MDC_CFG          (0x00c4)
#define REG_PMU_PAD_MAC_MDIO_CFG         (0x00c8)
#define REG_PMU_PAD_MAC_RXD0_CFG         (0x00d8)
#define REG_PMU_PAD_MAC_RXD1_CFG         (0x00dc)
#define REG_PMU_PAD_MAC_RXDV_CFG         (0x00e8)
#define REG_PMU_PAD_MAC_TXD0_CFG         (0x00f0)
#define REG_PMU_PAD_MAC_TXD1_CFG         (0x00f4)
#define REG_PMU_PAD_MAC_TXEN_CFG         (0x0100)
#define REG_PMU_PAD_GPIO_0_CFG           (0x010c)
#define REG_PMU_PAD_GPIO_1_CFG           (0x0110)
#define REG_PMU_PAD_GPIO_2_CFG           (0x0114)
#define REG_PMU_PAD_GPIO_3_CFG           (0x0118)
#define REG_PMU_PAD_GPIO_6_CFG           (0x0124)
#define REG_PMU_PAD_GPIO_7_CFG           (0x0128)
#define REG_PMU_PAD_GPIO_11_CFG          (0x0138)
#define REG_PMU_PAD_GPIO_12_CFG          (0x013c)
#define REG_PMU_PAD_GPIO_13_CFG          (0x0140)
#define REG_PMU_PAD_GPIO_14_CFG          (0x0144)
#define REG_PMU_PAD_UART_RX_CFG          (0x0148)
#define REG_PMU_PAD_UART_TX_CFG          (0x014c)
#define REG_PMU_PAD_CIS_SCL_CFG          (0x0150)
#define REG_PMU_PAD_CIS_SDA_CFG          (0x0154)
#define REG_PMU_PAD_SSI0_CLK_CFG         (0x0160)
#define REG_PMU_PAD_SSI0_TXD_CFG         (0x0164)
#define REG_PMU_PAD_SSI0_CSN_0_CFG       (0x0168)
#define REG_PMU_PAD_SSI0_RXD_CFG         (0x0170)
#define REG_PMU_PAD_SSI0_D_2_CFG         (0x011c)
#define REG_PMU_PAD_SSI0_D_3_CFG         (0x0120)
#define REG_PMU_PAD_SD0_CD_CFG           (0x0174)
#define REG_PMU_PAD_SD0_CLK_CFG          (0x017c)
#define REG_PMU_PAD_SD0_CMD_RSP_CFG      (0x0180)
#define REG_PMU_PAD_SD0_DATA_0_CFG       (0x0184)
#define REG_PMU_PAD_SD0_DATA_1_CFG       (0x0188)
#define REG_PMU_PAD_SD0_DATA_2_CFG       (0x018c)
#define REG_PMU_PAD_SD0_DATA_3_CFG       (0x0190)
#define REG_PMU_PAD_SADC_CH0_CFG         (0x0194)
#define REG_PMU_PAD_SADC_CH1_CFG         (0x0198)
#define REG_PMU_PAD_SADC_CH2_CFG         (0x019c)
#define REG_PMU_AXI0_PRIO_CFG0           (0x01b4)
#define REG_PMU_AXI0_PRIO_CFG1           (0x01b8)
#define REG_PMU_AXI1_PRIO_CFG0           (0x01bc)
#define REG_PMU_AXI1_PRIO_CFG1           (0x01c0)
#define REG_PMU_SWRSTN_NSR               (0x01c4)
#define REG_PMU_ARM_INT_0                (0x01e0)
#define REG_PMU_ARM_INT_1                (0x01e4)
#define REG_PMU_ARM_INT_2                (0x01e8)
#define REG_PMU_A625_INT_0               (0x01ec)
#define REG_PMU_A625_INT_1               (0x01f0)
#define REG_PMU_A625_INT_2               (0x01f4)
#define REG_PMU_DMA                      (0x01f8)
#define REG_PMU_WDT_CTRL                 (0x01fc)
#define REG_PMU_DBG_STAT0                (0x0200)
#define REG_PMU_DBG_STAT1                (0x0204)
#define REG_PMU_DBG_STAT2                (0x0208)
#define REG_PMU_DBG_STAT3                (0x020c)
#define REG_PMU_USB_SYS                  (0x0210)
#define REG_PMU_USB_CFG                  (0x0214)
#define REG_PMU_USB_TUNE                 (0x0218)
#define REG_PMU_PTSLO                    (0x022c)
#define REG_PMU_PTSHI                    (0x0230)
#define REG_PMU_PTSCTRL                  (0x0234)
#define REG_PMU_A625BOOT0                (0x2000)
#define REG_PMU_A625BOOT1                (0x2004)
#define REG_PMU_A625BOOT2                (0x2008)
#define REG_PMU_A625BOOT3                (0x200c)
#define REG_PMU_A625_START_CTRL          (0x2010)
#define REG_PMU_ARC_INTC_MASK            (0x2014)

//alias register
#define  REG_PMU_CLK_GATE            (REG_PMU_CLK_GATE0)
#define  REG_PMU_USER0               (REG_PMU_PTSCTRL)

/*ATTENTION: written by ARC */
#define PMU_ARM_INT_MASK                (REG_PMU_A625_INT_0)
#define PMU_ARM_INT_RAWSTAT             (REG_PMU_A625_INT_1)
#define PMU_ARM_INT_STAT                (REG_PMU_A625_INT_2)

#define PMU_A625_INT_MASK               (REG_PMU_ARM_INT_0)
#define PMU_A625_INT_RAWSTAT            (REG_PMU_ARM_INT_1)
#define PMU_A625_INT_STAT               (REG_PMU_ARM_INT_2)


/* SWRST_MAIN_CTRL */
#define PTS_RSTN_BIT            (0)
#define TMR_RSTN_BIT            (1)
#define PIXEL_RSTN_BIT          (2)
#define SADC_RSTN_BIT           (3)
#define PWM_RSTN_BIT            (4)
#define EFUSE_RSTN_BIT          (5)
#define ACODEC_RSTN_BIT         (6)
#define I2C2_RSTN_BIT           (7)
#define I2C1_RSTN_BIT           (8)
#define I2C0_RSTN_BIT           (9)
#define UART2_RSTN_BIT          (10)
#define UART1_RSTN_BIT          (11)
#define UART0_RSTN_BIT          (12)
#define SPI1_RSTN_BIT           (13)
#define SPI0_RSTN_BIT           (14)
#define GPIO0_DBRSTN_BIT        (15)
#define DDRC_RSTN_BIT           (16)
#define DDRPHY_RSTN_BIT         (17)
#define ARC_RSTN_BIT            (18)
#define UTMI_RSTN_BIT           (19)
#define I2S_RSTN_BIT            (20)
#define GPIO1_DBRSTN_BIT        (21)
#define ISP_ARSTN_BIT           (22)
#define TAE_ARSTN_BIT           (23)
#define JPG_ARSTN_BIT           (24)
#define BGM_ARSTN_BIT           (25)
#define CPU_RSTN_BIT            (30)
#define SYS_RSTN_BIT            (31)

/* SWRST_AHB_CTRL */
#define AHBBUS_HRSTN_BIT        (0)
#define TAE_HRSTN_BIT           (1)
#define JPEG_HRSTN_BIT          (2)
#define BGM_HRSTN_BIT           (3)
#define ISP_HRSTN_BIT           (4)
#define EMC_HRSTN_BIT           (5)
#define ARC_HRSTN_BIT           (6)
#define INTC_HRSTN_BIT          (7)
#define AES_HRSTN_BIT           (8)
#define USB_HRSTN_BIT           (9)
#define EMAC_HRSTN_BIT          (10)
#define SDC1_HRSTN_BIT          (11)
#define SDC0_HRSTN_BIT          (12)
#define DMAC1_HRSTN_BIT         (13)
#define DMAC0_HRSTN_BIT         (14)
#define DDRC_HRSTN_BIT          (15)

#define FH_GMAC_SPEED_100M					(1<<2)
#define FH_GMAC_AHB_RESET					(1<<EMAC_HRSTN_BIT)
#define PMU_RMII_SPEED_MODE (REG_PMU_CLK_SEL)
#define PMU_RXDV_GPIO_SWITCH (REG_PMU_PAD_MAC_RXDV_CFG)
#define PMU_RXDV_GPIO_MASK (0x03000000)
#define PMU_RXDV_GPIO_VAL (0x01000000)

#define PMU_DWI2S_CLK_SEL_REG   (REG_PMU_I2SCLK_CTRL)
#define PMU_DWI2S_CLK_SEL_SHIFT (0)
#define PMU_DWI2S_CLK_DIV_REG   (REG_PMU_I2SCLK_CTRL)
#define PMU_DWI2S_CLK_DIV_SHIFT (4)

#define PMU_PIX_MODE_SEL        (16)

#define USB_UTMI_RST_BIT      (0x1<<19)
#define USB_PHY_RST_BIT       (0x11)
#define USB_SLEEP_MODE_BIT    (0x1<<24)
#define USB_IDDQ_PWR_BIT      (0x1<<31)
#define USB_TUNE_ADJ_SET	(0x78203344)


/* because chips with some same function in different */
/* pmu register, use wrap marco to make code to be same */
#define PMU_RMII_SPEED_MODE (REG_PMU_CLK_SEL)
#define REG_PMU_USB_SYS1 (REG_PMU_USB_SYS)

#define MEM_START_PHY_ADDR	DDR_BASE
#define MEM_SIZE			0x4000000




#define PMU_IRQ			0
#define DDRC_IRQ		1
#define WDT_IRQ			2
#define TMR0_IRQ		3
#define PAE_IRQ			4
#define ISP_IRQ			5
#define BGM_IRQ			7
#define JPEG_IRQ		8
#define I2C0_IRQ		9
#define I2C1_IRQ		10
#define I2C2_IRQ		11
#define I2S0_IRQ		12
#define GMAC_IRQ		13
#define SDC0_IRQ		14
#define SDC1_IRQ		15
#define SPI1_IRQ		16
#define SPI0_IRQ		17
#define UART0_IRQ		18
#define UART1_IRQ		19
#define UART2_IRQ		20
#define DMAC0_IRQ		21
#define DMAC1_IRQ		22
#define ACW_IRQ			23
#define AES_IRQ			24
#define SADC_IRQ		25
#define GPIO0_IRQ		26
#define USBC_IRQ		27
#define ARM_SW_IRQ		28
#define ALARM_IRQ		29
#define ARC_SW_IRQ		32
#define RTC_IRQ			33
#define PWM_IRQ			36
#define MIPIC_IRQ		37
#define MIPI_WRAP_IRQ	38
#define GPIO1_IRQ		40
#define USBC_IDHV_IRQ	41
#define USBC_OTG_IRQ	42
#define USBC_DP_IRQ		43
#define USBC_DM_IRQ		44


/* Specific Uart Number */
#define FH_UART_NUMBER 3



/* SWRST_MAIN_CTRL */
#define PTS_RSTN_BIT			(0)
#define TMR_RSTN_BIT			(1)
#define PIXEL_RSTN_BIT			(2)
#define SADC_RSTN_BIT			(3)
#define PWM_RSTN_BIT			(4)
#define EFUSE_RSTN_BIT			(5)
#define ACODEC_RSTN_BIT			(6)
#define I2C2_RSTN_BIT			(7)
#define I2C1_RSTN_BIT			(8)
#define I2C0_RSTN_BIT			(9)
#define UART2_RSTN_BIT			(10)
#define UART1_RSTN_BIT			(11)
#define UART0_RSTN_BIT			(12)
#define SPI1_RSTN_BIT			(13)
#define SPI0_RSTN_BIT			(14)
#define GPIO0_RSTN_BIT			(15)
#define DDRC_RSTN_BIT			(16)
#define DDRPHY_RSTN_BIT			(17)
#define ARC_RSTN_BIT			(18)
#define UTMI_RSTN_BIT			(19)
#define I2S_RSTN_BIT			(20)
#define GPIO1_RSTN_BIT		(21)
#define ISP_ARSTN_BIT			(22)
#define TAE_ARSTN_BIT			(23)
#define JPG_ARSTN_BIT		(24)
#define BGM_ARSTN_BIT		(25)
#define CPU_RSTN		(30)
#define SYS_RSTN_BIT			(31)

/* SWRST_AHB_CTRL */
#define AHBBUS_HRSTN_BIT			(0)
#define TAE_HRSTN_BIT			(1)
#define JPG_HRSTN_BIT			(2)
#define BGM_HRSTN_BIT			(3)
#define ISP_HRSTN_BIT			(4)
#define EMC_HRSTN_BIT			(5)
#define ARC_HRSTN_BIT			(6)
#define INTC_HRSTN_BIT			(7)
#define AES_HRSTN_BIT			(8)
#define USB_HRSTN_BIT			(9)
#define EMAC_HRSTN_BIT			(10)
#define SDC1_HRSTN_BIT			(11)
#define SDC0_HRSTN_BIT			(12)
#define DMAC1_HRSTN_BIT				(13)
#define DMAC0_HRSTN_BIT				(14)
#define DDRC_HRSTN_BIT			(15)

/* SWRST_APB_CTRL */
#define TMR_PRSTN_BIT		(0)
#define MIPIC_PRSTN_BIT			(1)
#define MIPIW_PRSTN_BIT			(2)
#define PWM_PRSTN_BIT			(3)
#define RTC_PRSTN_BIT			(4)
#define EFUSE_PRSTN_BIT			(5)
#define SADC_PRSTN_BIT			(6)
#define ACODEC_PRSTN_BIT		(7)
#define I2S_PRSTN_BIT			(8)
#define GPIO1_PRSTN_BIT			(9)
#define GPIO0_PRSTN_BIT			(10)
#define SPI1_PRSTN_BIT			(11)
#define SPI0_PRSTN_BIT			(12)
#define UART2_PRSTN_BIT			(13)
#define UART1_PRSTN_BIT			(14)
#define UART0_PRSTN_BIT			(15)
#define I2C2_PRSTN_BIT      	(16)
#define I2C1_PRSTN_BIT			(17)
#define I2C0_PRSTN_BIT      	(18)
#define WDT_PRSTN_BIT      	    (19)

/* FH Serial HardWare HandShake */
#define UART1_TX_HW_HANDSHAKE   (9)
#define UART1_RX_HW_HANDSHAKE   (8)
#define UART1_DMA_TX_CHAN       (2)
#define UART1_DMA_RX_CHAN       (3)

#endif /* _FH8626V100_H_ */
